1. Field of the Invention
This invention relates to a semiconductor memory device, and specifically relates to a non-volatile semiconductor memory (EEPROM) having a cell array with NAND cell units arranged therein.
2. Description of the Related Art
A NAND-type flash memory is known as one of EEPROMs. A NAND-type flash memory is formed of NAND cell units, in each of which plural memory cells are connected in series in such a way that adjacent two memory cells share a source/drain diffusion layer. Disposed at both ends of each NAND cell unit are first and second select gate transistors for selectively coupling the NAND cell unit to a bit line and a source line, respectively.
A memory cell in the NAND cell unit is a MOS transistor with a floating gate serves as a charge storage layer and a control gate stacked thereabove. Control gates of memory cells are patterned to be a word line, which is continued in one direction. The gates of the first and second select gate transistors are patterned to be a first and second select gate line, which are disposed in parallel with the word line.
Each bit line is formed to be continued as crossing the word lines and contacted with the drain diffusion layer of the first select gate transistor. The source side of the NAND cell unit (i.e. the source diffusion layer of the second select gate transistor) is coupled to a common source line.
A set of NAND cell units sharing a word line constitutes a “block”, which usually serves as a unit of data erase. Usually, plural blocks are arranged in the bit line direction to share a bit line. In this case, plural blocks are arranged in such a manner that first and second blocks disposed adjacent to each other share bit line contacts, and second and third blocks disposed adjacent to each other share a source line contacts. In other words, adjacent two first select gate lines in the adjacent two blocks sandwiching the bit line contacts are disposed adjacent to each other while adjacent two second select gate lines in the adjacent two blocks sandwiching the source line contacts are disposed adjacent to each other.
As the miniaturization and high integration of the cell array are advanced more; and the word line made longer and narrower, the word line delay becomes larger. To achieve a high speed performance in spite of the word line delay, it is desired to make the first and second select gate lines sufficiently low resistive, and use such a scheme that an on-drive timing of either one of them serves as a reference timing for data sensing. Word line charge-up starting prior to the reference timing, the influence of the word line delay will be removed.
To achieve the above-described read timing control, it is required of the first and second select gate lines with the same stacked polysilicon films as the word line to be made low resistive. For this purpose, two methods will be used as follows: one is to make the width of the select gate lines larger than the word line; and the other is to form shunt wirings, which are formed of a metal film, for backing the first and second select gate lines.
As a shunt wiring structure used for the first and second select gate lines, there has been provided such a manner that shunt wirings of the first select gate lines on the bit line contact side (i.e., drain side) are formed to have a common connection portion serving as a shunt portion shared by adjacent blocks while shunt wirings of the second select gate lines on the source line contact side (i.e., source side) are formed independent of each other for adjacent blocks (refer to Unexamined Japanese Patent Application Publication No. 2001-308206).
The reason of that the shunt wiring structures of the first and second select gate lines are made different from each other is for certainly avoiding such a situation that unnecessary bit line currents are carried in non-selected blocks. That is, in case of such a specification that on/off of the second select gate line determines connection/disconnection between the bit line and the NAND cell unit, the second select gate lines in the adjacent blocks are formed as independent of each other, and these are controlled in potential independently of each other. As described above, the second select gate lines being formed independent of each other, even if adjacent two first gate lines are short-circuited, it will be avoided that unnecessary bit line currents flow in the non-selected block.